The document "Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers", New York, Oct. 7-10, 1985, pp. 359-362; S. Steinlechner, and our prior French patent application number 87 03758 filed Mar. 18, 1987 (and our corresponding U.S. patent application Ser. No. 167,787) describe a binary calculation circuit of the type comprising at least one cell having:
a 1-bit first input for receiving a first input signal (Ai);
a 1-bit second input for receiving a second input signal (Bi);
a 1-bit carry-in input for receiving a carry-in signal (Ri-1 S);
first means for generating an exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi) from the first and second input signals;
second means for producing a result signal by performing an exclusive-OR function between the carry-in signal (Ri-1 S) said exclusive-OR signal (Ai.sym.Bi);
third means for producing a carry-out signal (Ri S) by performing a transmission function by means of two transmission gates controlled by said exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), with one of the gates passing the carry-in signal (Ri-1 S) and the other gate passing one or other of the two input signals (Ai, Bi).
In the embodiments described in the earlier patent application, the carry-in signal (Ri-1 S) is applied to the drains of the transistors equipping the transmission gates under the control of said exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi). This gives rise to a loss of time during calculation of the carry-out signal (Ri S) and consequently to a loss of carry propagation time in circuits comprising a plurality of cells in parallel organized as adder and/or subtracter modules with propagated carry.
The Applicants have now observed that by interchanging the roles of the second input signal (Bi) and the carry-in signal (Ri-1 S), and by using the intermediate variables thus obtained by said interchange for calculating the carry-out signal (Ri S), the carry propagation delay in such parallel-connected cells is considerably reduced. The carry-in signal (Ri-1 S) passing via the exclusive-OR signal (Ai.sym.Ri-1 S) is now applied directly to the grids of the transistors in the transmission gates which are controlled by said exclusive-OR signal (Ai.sym.Ri-1 S) and its complement (Ai.sym.Ri-1 S).